The present invention relates generally to a stack-gate flash memory cell and its memory array and particularly to a scalable stack-gate flash memory cell and its contactless memory array.
The stack-gate flash memory cell is known to be a one-transistor cell, in which the gate length of a cell can be defined by using a minimum-feature-size (F) of technology used. Therefore, the stack-gate flash memory cell is often used in existing high-density memory system. The stack-gate flash memory cells can be interconnected in series to form a high-density NAND-type array with common-source/drain diffusion regions. However, the read speed is relatively slow for a NAND-type array due to the series resistance of the configuration. Moreover, a NAND-type flash memory cell is programmed by Fowler-Nordheim tunneling across the thin tunneling-oxide layer between the floating-gate and the common-source/drain diffusion region and its programming speed is relatively slow. In addition, when the gate length of a stack-gate flash memory cell in a NAND-type array is further scaled down, the junction depth of common-source/drain diffusion regions must be scaled accordingly, and the overlapped region between the floating gate and the common-source/drain diffusion region becomes smaller, resulting in a further slow process for programming, reading and erasing.
The stack-gate flash memory cells can be connected with the common-source diffusion lines and the common-drain diffusion regions in each column being connected to a bit-line through contacts for a NOR-type flash memory array. The read speed of a NOR-type memory array is much faster as compared to that of a NAND-type flash memory array. A stack-gate flash memory cell in a NOR-type flash memory array is in general programmed by channel hot-electron injection and its programming speed is much faster than that of a NAND-type flash memory array; however, the programming power is large and the programming efficiency is low. Moreover, as the gate length of a stack-gate flash memory cell is further scaled, the punch-through effect becomes a major concern for channel hot-electron injection as a programming method. In addition, the cell size of a NOR-type flash memory array is about twice that of a NAND-type flash memory array due to the bit-line contacts.
A typical contactless flash memory array taking advantages of a NAND-type and a NOR-type architecture is shown in FIG. 1, in which a plurality of bit lines (BL0xcx9cBL6) are formed in parallel by using the common buried diffusion lines; the stack-gate flash memory cells (100xcx9c129) in each column are arranged between the bit lines; the control-gates in each row are connected to form a word line and a plurality of word lines are formed perpendicularly to the plurality of bit lines. It is clearly seen that the cell size of FIG. 1 can be made to be comparable with that of a NAND-type array due to the contactless structure used; the read speed of FIG. 1 is better than that of a NAND-type array and is inferior to that of a NOR-type array due to the larger bit-line capacitance with respect to the semiconductor substrate; and the programming speed of FIG. 1 is much faster than that of a NAND-type array and is comparable to that of a NOR-type array due to the channel hot-electron injection as a programming method. A typical example for implementing a high-density memory array shown in FIG. 1 may refer to U.S. Pat. No. 5,654,917. Basically, there are several issues appeared in the manufacture of this array architecture: the stack-gate structure in the channel-width direction must be etched to have an independent floating-gate for each cell without trenching the common buried diffusion bit-lines and the semiconductor substrate between the word lines; the isolation of cells between the neighboring word lines is performed by ion-implantation without increasing the buried bit-line junction capacitance and reducing the cell width; the gate length of the stack-gate flash memory cell is difficult to be scaled down further due to the punch-through effect; the junction depth of the common buried diffusion bit-lines can""t be easily scaled down without increasing the bit-line resistance and further decreasing the read/erasing speed; and higher parasitic capacitance between the word lines and the common buried diffusion bit lines must be reduced.
A scalable stack-gate flash memory cell of the present invention is formed on a shallow-trench-isolation (STI) structure being formed on a semiconductor substrate of a first conductivity type. The shallow-trench-isolation structure comprises an active region being formed between two parallel STI regions, in which a first conductive layer being formed on a thin tunneling-dielectric layer is located in the active region and the raised filed-oxide (FOX) layer is formed on each of parallel STI regions. A scalable stack-gate flash memory cell can be divided into three regions: a common-source region, a gate region, and a common-drain region, in which the gate region is located between the common-source region and the common-drain region. The gate region comprises a stack-gate structure with its gate length being defined by a fourth sidewall dielectric spacer formed over a sidewall of the common-source region and is further divided into two subregions: a low threshold-voltage stack-gate region and a high threshold-voltage stack-gate region, in which the low threshold-voltage stack-gate region comprises a stack-gate transistor being formed on a low doping semiconductor substrate with a stack-gate length being defined by a third sidewall dielectric spacer formed over the same sidewall of the common-source region; the high threshold-voltage stack-gate region comprises a stack-gate transistor being formed on an implanted semiconductor substrate and is located near the common-drain region. An implanted region being formed under the thin tunneling-dielectric layer of a high threshold-voltage stack-gate region comprises a shallow implant region of a first conductivity type for threshold-voltage adjustment and a deep implant region of a first conductivity type for forming a punch-through stop. The common-source region comprises a common-source diffusion region of a second conductivity type being implanted with doping impurities in a self-aligned manner into a semiconductor substrate of the active region, a first flat bed being formed by a common-source diffusion region and the first etched raised field-oxide layers, a first sidewall dielectric spacer being formed over a sidewall of the gate region and on a portion of the first flat bed, a common-source conductive bus line capped with a first metal-silicide layer being formed over the first flat bed outside of the first sidewall dielectric spacer, and a first planarized thick-oxide layer being formed over the first sidewall dielectric spacer and the first metal-silicide layer. The common-drain region comprises a common-drain diffusion region of a second conductivity type being implanted with doping impurities in a self-aligned manner into a semiconductor substrate of the active region, a second flat bed being formed by a common-drain diffusion region and the second etched raised field-oxide layers, a second sidewall dielectric spacer being formed over a sidewall of the gate region and on a portion of the second flat bed, a common-drain conductive bus line capped with a second metal-silicide layer being formed over the second flat bed outside of the second sidewall dielectric spacer, and a second planarized thick-oxide layer being formed over the second sidewall dielectric spacer and the second metal-silicide layer. The control gate together with a first interconnect metal layer being acted as a word line is patterned transversely to the common-source/drain conductive bus line and etched simultaneously by a hard masking layer being formed by a masking dielectric layer being aligned above the active region and its two sidewall dielectric spacers.
A contactless scalable stack-gate flash memory array of the present invention comprises a plurality of parallel shallow-trench-isolation (STI) regions and a plurality of active regions being formed alternately on a semiconductor substrate of a first conductivity type, wherein each of the plurality of parallel STI regions is filled with a raised field-oxide layer and each of the plurality of active regions is filled with a floating-gate layer being formed on a thin tunneling-dielectric layer; a plurality of virtual gate regions and a plurality of common-source bus-line regions being alternately formed by a masking photoresist step and being transversely to the plurality of parallel STI regions, wherein each of the plurality of virtual gate regions is divided into three regions: two scalable stack-gate regions being located in each side portion and a common-drain region being located between the two scalable stack-gate regions; and a plurality of word lines being formed transversely to the plurality of common-source/drain bus-line regions and above the plurality of active regions, wherein each of the plurality of word lines is connected to the control-gates of the scalable stack-gate regions in each row. The scalable stack-gate region comprises a plurality of scalable stack-gate flash memory cells in each column, wherein each of the plurality of scalable stack-gate flash memory cells is affordmentioned. Each of the plurality of common-source bus-line regions comprises a plurality of common-source diffusion regions of a second conductivity type being formed by implanting doping impurities in a self-aligned manner into the semiconductor substrate of the plurality of active regions along the common-source bus-line region; a first flat bed being formed alternately by a common-source diffusion region and a first etched raised field-oxide layer; a pair of first sidewall dielectric spacers being formed over the sidewalls of the neighboring virtual gate regions and on a portion of the first flat bed; a common-source conductive bus line being formed over the first flat bed between the pair of first sidewall dielectric spacers; a first metal-silicide layer being formed over the common-source conductive bus line; and a first planarized thick-oxide layer being formed over the first metal-silicide layer and the pair of first sidewall dielectric spacers. The common-drain bus-line region comprises a plurality of common-drain diffusion regions of a second conductivity type being formed by implanting doping impurities in a self-aligned manner into the semiconductor substrate of the plurality of active regions along each of the common-drain bus-line regions; a second flat bed being formed alternately by a common-drain diffusion region and a second etched raised field-oxide layer; a pair of second sidewall dielectric spacers being formed over the sidewalls of the neighboring scalable stack-gate regions and on a portion of the second flat bed; a common-drain conductive bus line being formed over the second flat bed between the pair of second sidewall dielectric spacers; a second metal-silicide layer being formed over the common-drain conductive bus line; and a second planarized thick-oxide layer being formed over the second metal-silicide layer and the pair of second sidewall dielectric spacers. Each of the plurality of word lines comprises a first interconnect metal layer being integrated with a plurality of control-gates in each row and is patterned and etched simultaneously with the plurality of control-gates by a hard masking layer being formed by a masking dielectric layer being aligned to the active region and its two sidewall dielectric spacers.